Ofertes d'ocupació per a Perl

• Nivell d'experiència---
• Tipus de contracteA temps complert
• Publicada24 d’oct.

. API Python OOP Jenkins Linux Git DevOps Perl

Monolithic Power Systems, Inc. (MPS) is one of the fastest growing companies in the Semiconductor industry. We are worldwide technical leaders in Integrated Power Semiconductors and Systems Power delivery architectures. At MPS, we cultivate creativity, are passionate about sustainability, and are committed to providing leading-edge products and innovation to our customers. Our portfolio of technology helps power our world ---come join our team and see how YOU can make a difference.

Job Description

Job Summary:

A Sr. Digital R&D & Automation Engineer works in the design and development of tools and scripts, automation of tasks, definition and implementation of new standard development flows and methodologies, configuration and maintenance of industry standard EDA tools for digital/mixed-signal ICs design for leading edge technologies, among other tasks. Products include switching regulators, display drivers, audio amplifiers, precision linear circuits and power management ICs for fast-growing portable and non-portable markets such as broadband modems, PDAs, notebooks, cell phones, telecom, fiber optics, digital camera, and network equipment.

 If you have a solid software background and interest in supporting semiconductor chip design, this is the job for you.

 

Essential Functions

• Scripting of ASIC Mixed-Signal Design Tools and automation for different Teams (Digital Design, Physical, Verification, DFT, Mixed-Signal, etc.).
• R&D of new Methodologies, Flows, Tools, IPs, and Licenses.
• Work on R&D Tasks related to any of the ASIC IC Design flow stages.
• Define, implement and automate new standard flows and methodologies, and improve existing ones.
• Development of continuous integration plus continuous delivery environment applied to IC design.
• Linux system administration to install, build, test and develop new environments/tools/scripts.
• Troubleshoot problems related to machine, network and tools.
• Document processes and flows.
• Work closely with the Digital, CAD and IT Teams.
• Work on and support projects in any of the ASIC flow stages.
  
  

• Knowledge and experience in Unix/Linux admin and networking
• Proficiency in scripting languages (Tcl, Perl, Python, csh, etc.) and OOP.
• Familiar with revision control tools (Git, GitLab, etc.)
• Excellent verbal, written communication and interpersonal skills.
• Experience in system administration and supporting/installation of CAD tools.
• BSEE/BSCS or equivalent (MSEE/MSCS preferred)
• DevOps knowledge and experience (CI, CD, pipelines, Jenkins, GitlabCI, etc)
• Is a plus:
• Basic Digital Design and Verilog/SystemVerilog knowledge.
• Knowledge of the ASIC Design Flow.
• Knowledge related to AI usage for developments (LLMs, MCPs, AI Agents, AI Agent harness, etc.).
• API client development.
• Unit and integration testing
  
  

• Nivell d'experiència---
• Tipus de contracteA temps complert
• Publicada13 d’oct.

. Python Perl

We are seeking an experienced SoC Physical Verification Engineer to drive physical verification signoff for next-generation logic, memory-centric SoCs, and advanced-node designs. The candidate will be responsible for ensuring tapeout-ready silicon through comprehensive DRC, LVS, ERC, PERC, DFM, reliability verification, and manufacturability signoff, while collaborating closely with Physical Design, CAD, RTL, Product Engineering, EDA vendors, and foundry teams.

This role requires a strong hands-on technical leader who can drive methodology, execution, and signoff while collaborating closely with Architecture, BUMP, RDL routing and PD team collaboration.

Key Responsibilities

· Own and drive full-chip and hierarchical / block physical verification signoff, including DRC, LVS, ERC, PERC, Antenna, DFM, Density, Metal Fill, CMP, and Reliability Checks.

• Debug, customize, and deploy foundry-qualified rule decks, manage waivers, and ensure clean signoff closure for advanced-node designs.

• Perform reliability verification including ESD, Latch-up, Electromigration (EM), Floating Nets, Multi-Power Domain, and Connectivity Checks.

• Support parasitic RC extraction and correlation of verification results with implementation and silicon measurements.

• Develop and maintain physical verification automation, regression infrastructure, scripting frameworks, and AI-assisted workflows.

• Work closely with PD, CAD, RTL, Product Engineering, EDA vendors, and foundries (including direct TSMC interaction) from project kick-off through tapeout.

Required / Preferred Qualifications

· Experience in full-chip or block-level physical verification for advanced-node SoCs, memory, or heterogeneous integration designs.

• Strong expertise in DRC, LVS, ERC, PERC, DFM, Antenna, Reliability Verification, and Physical Verification Signoff Methodologies.

• Experience in advanced technology nodes including 22nm, 16nm, 7nm, 5nm, and below.

• Good understanding of RTL-to-GDSII implementation flows, extraction methodologies, and physical design impacts on verification closure.

• Strong debugging, analysis, and cross-functional collaboration skills.

• Familiarity with AI-assisted development and verification workflows.

• Experience with DRAM, Memory-Centric SoCs, Chiplets, 2.5D/3D IC Integration.

• Background in CPU, GPU, High-Performance Computing Designs.

• Knowledge of advanced-node FEOL/BEOL rules, foundry design manuals, and DFM methodologies.

• Exposure to post-silicon debug, yield analysis, and silicon correlation activities.

• MS/PhD in Electrical Engineering, Computer Engineering, or related field.

• Experience developing automation using Python, Tcl, Perl, or similar scripting languages

Tools Required

· Physical Verification: Mentor Calibre (DRC, LVS, ERC, PERC, DFM), Synopsys IC Validator (ICV), Cadence Pegasus.

· Implementation & Extraction: Synopsys ICC2/Fusion Compiler, Cadence Innovus, Synopsys StarRC, Cadence Quantus.

· Automation & Analysis: Python, Tcl, Perl, AI/ML-enabled verification frameworks, and regression infrastructure development tools.