We are seeking an experienced SoC Physical Verification Engineer to drive physical verification signoff for next-generation logic, memory-centric SoCs, and advanced-node designs. The candidate will be responsible for ensuring tapeout-ready silicon through comprehensive DRC, LVS, ERC, PERC, DFM, reliability verification, and manufacturability signoff, while collaborating closely with Physical Design, CAD, RTL, Product Engineering, EDA vendors, and foundry teams.

This role requires a strong hands-on technical leader who can drive methodology, execution, and signoff while collaborating closely with Architecture, BUMP, RDL routing and PD team collaboration.

Key Responsibilities

· Own and drive full-chip and hierarchical / block physical verification signoff, including DRC, LVS, ERC, PERC, Antenna, DFM, Density, Metal Fill, CMP, and Reliability Checks.

• Debug, customize, and deploy foundry-qualified rule decks, manage waivers, and ensure clean signoff closure for advanced-node designs.

• Perform reliability verification including ESD, Latch-up, Electromigration (EM), Floating Nets, Multi-Power Domain, and Connectivity Checks.

• Support parasitic RC extraction and correlation of verification results with implementation and silicon measurements.

• Develop and maintain physical verification automation, regression infrastructure, scripting frameworks, and AI-assisted workflows.

• Work closely with PD, CAD, RTL, Product Engineering, EDA vendors, and foundries (including direct TSMC interaction) from project kick-off through tapeout.

Required / Preferred Qualifications

· Experience in full-chip or block-level physical verification for advanced-node SoCs, memory, or heterogeneous integration designs.

• Strong expertise in DRC, LVS, ERC, PERC, DFM, Antenna, Reliability Verification, and Physical Verification Signoff Methodologies.

• Experience in advanced technology nodes including 22nm, 16nm, 7nm, 5nm, and below.

• Good understanding of RTL-to-GDSII implementation flows, extraction methodologies, and physical design impacts on verification closure.

• Strong debugging, analysis, and cross-functional collaboration skills.

• Familiarity with AI-assisted development and verification workflows.

• Experience with DRAM, Memory-Centric SoCs, Chiplets, 2.5D/3D IC Integration.

• Background in CPU, GPU, High-Performance Computing Designs.

• Knowledge of advanced-node FEOL/BEOL rules, foundry design manuals, and DFM methodologies.

• Exposure to post-silicon debug, yield analysis, and silicon correlation activities.

• MS/PhD in Electrical Engineering, Computer Engineering, or related field.

• Experience developing automation using Python, Tcl, Perl, or similar scripting languages

Tools Required

· Physical Verification: Mentor Calibre (DRC, LVS, ERC, PERC, DFM), Synopsys IC Validator (ICV), Cadence Pegasus.

· Implementation & Extraction: Synopsys ICC2/Fusion Compiler, Cadence Innovus, Synopsys StarRC, Cadence Quantus.

· Automation & Analysis: Python, Tcl, Perl, AI/ML-enabled verification frameworks, and regression infrastructure development tools.